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Programmable Logic Devices (PLDs) have not only become extremely popular, they now are the accepted norm in new logic designs. The 'traditional' PLD design tools included CUPL, ABEL, MPASM and other rather low level input tools. Nowadays, PROTEL, P-CAD, HyperSignal, Viewlogic, ALDEC and many other vendors provide higher level design, simulation and verification tools. The current "Hot" PLD design methodology uses VHDL, a C-like programming language that provides a great deal simplification to the design process. VHDL is also supported in various versions by a growing number of vendors with a myriad of new and very useful tools. This page provides links to VHDL, State Machine and other design / analytical PLD Tools.

For more information on PLDs, check out our Programmable Logic Device page, with information on manufacturers, articles, reference books, and more.

 

Contents of This Page:

VHDL Information
Other PLD Language Information
State Machine Tools
PLD Tools Application Examples






 
VHDL Information


ALDEC



CYPRESS

CYPRESS has Warp low cost VHDL software, but is no longer providing direct support. Press Products, then Programmable Logic, then either of the subordinate links to see what they have now and how to get Warp and Warp support nowadays.


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Other PLD Language Information


ATMEL

ATMEL has their versions of ABEL, CUPL and Synario available for FREE download!



ALTERA

ALTERA has some nice design software -- take a look!


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State Machine Tools


ALDEC

Download ALDEC's State Machine Editor Tutorial

Download ALDEC's State Machine Editor User Guide


Download ALDEC's State Machine Editor


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PLD Tools Application Example Links


CYPRESS

CYPRESS has some design support articles and application notes here.


Focus Report: PLD Tools, by Peggy Aycinena for ISD Magazine, September 2000. Programmable logic devices are hot these days - and there's a lot of tool offerings out there helping to make them happen.

Verilog Simulation Bridges the Gap Between PLDs and ASICs, by Allen Vexler for ISD Magazine, August 1999. Designers used a Verilog simulator and an ASIC design flow to create a PLD that would emulate an ASIC, enabling faster and more accurate verification and testing.

Emerging Trends in PLD Tools, by Martin S. Won and Balaji Thirumalai for ISD Magazine, August 1999. Process advances and new design methodologies push programmable logic tool vendors to extend tools to accommodate multiple processors, widely dispersed workgroups, and Web support.

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