From the very First SSS "Technical Tricks" Column
April 1, 1992
The very first technical column comes from your Publisher's toolkit. Ever need
a simple, quick and dirty PN generator for data scrambling, direct sequence PN
use or to pick "semi-random" hop frequencies? Then here is one tried and true
as well as foolproof method that requires no EPROM or PLD programmer (or software either.)
Simple, short length (4 to 13 stage)maximal length shift register (MLSR)
sequence generators are often used to provide simple PN code generators for
SS systems. These simple generators usually perform very well when started
from the correct initial conditions or when reset at power up. However, most of
these simple circuits can hang up and stop generating anything (they can get stuck)
when an all ones (or an all zeros) condition occurs. Which condition that causes hang up or
how it got to this condition is immaterial - the darn thing is broke when this
happens! The circuit concept shown in figure 1 solves this problem very nicely
and even includes an EPOCH sync detector as well (for data timing, scope sync, or whatever.)
The circuit of figure 1 is a very simple 5 stage (length 31) MLSR PN generator
that could be used under the new Ham STA (it has been used commercially by
a Japanese-American company.) It is built from two 74HC175 shift registers,
one 74HC86 and two 74HC30 nand gates. As shown, the generator uses
feedback from the last shift register stage as well as from the second shift
register stage. This connection, when started from the all zero's state will
always generate the correct MLSR sequence. The top nand gate looks for
the occurrence of an all one's condition (an indication of being stuck) and resets
the shift registers to all zero's if this condition should ever occur. The
bottom nand gate detects the occurrence of the all zero's condition which marks
the start of a PN cycle of length 31 - also known as a PN EPOCH.
This same idea will work with virtually any size PN generator made from a
MLSR sequence. Simply decode both all one's and all zero's states, use them
correctly and Voila!
The speed capability of this circuit is pretty high. Since the design is fully
static, there is no low frequency limit - it could be as slow as a chip per day or so.
It can run as fast as the accumulated delays down the shift register / EXOR
chain. in the 5 stage design shown here, be careful running this design much
beyond 10 MHz. Faster speeds are possible with F-speed logic substituted
for the HC parts shown. Still greater speeds are possible with ECL / ACL or
AHC implementations. However, to really go above say
30 MHz, a clever design might use a small ECL RAM as a re-circulating
delay line and tap off the PN as desired. The RAM could be loaded at power up
by a host micro-processor through a serial or parallel I/O.
Questions, comments or suggestions on anything covered in this column are
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